Journal Publications
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Relative Performance Measures of Portfolio Robustness (with Andrew Lim and J. George Shanthikumar),
in preparation
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Competitive Analysis Approach to Robust Portfolio Choice Problems (with Andrew Lim and J. George Shanthikumar),
in preparation
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Robust Multi-Product Dynamic Pricing (with Andrew Lim and J. george Shanthikumar),
in preparation
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Optimal Investment and Consumption with Event Risk (with Andrew Lim),
under review
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Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design
(with Mongkol Ekpanyapong, Jacob Minz, Hsien-Hsin S. Lee, and Sung Kyu Lim),
To appear in IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems, 2006.
Refereed Conference Preceedings
Abstracts
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Optimal Investment and Consumption with Event Risk (with Andrew Lim).
This paper concerns the problem of optimal
investment and consumption, with power utility, discontinuous
price processes, and regime switching. Regime switching is
modelled by a finite state Markov chain, but unlike traditional
regime switching models, changes in regime may be
accompanied by jumps in the asset price at the instant of
transition, where the distribution of the jump sizes are
conditional on the regime before and after the transition. This
enables us to model a situation where a transition from a 'good'
regime to a 'bad' one (for instance) is likely to be accompanied
by a downward jump in the price, while transitions from a 'bad'
regime to a 'good' one is likely to be accompanied by an upward
jump. Alternatively, such a model may be regarded as a
partial approximation to a stochastic parameter price model, and
as such, gives rise to a tractable method for finding elegant
near-optimal solutions to investment-consumption problems
associated with such models. Expressions for the optimal
investment portfolio and consumption policy are obtained using
stochastic control methods. It is shown that regime switching
models with jumps at the instant of transition have optimal
solutions that are significantly different from those associated
with traditional regime switching models where changes in regime
are typically not accompanied by jumps.
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Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design
(with Mongkol Ekpanyapong, Jacob Minz, Hsien-Hsin S. Lee, and Sung Kyu Lim).
As process technology migrates to deep submicron with feature size
less than 100nm, global wire delay is becoming a major hindrance in
keeping the latency of intra-chip communication within a single cycle,
thus decaying the performance scalability substantially.
An effective floorplanning algorithm can no longer ignore the
information of dynamic communication patterns of applications. In this
paper, using the profile information acquired at the architecture/microarchitecture
level, we propose a ''profile-guided microarchitectural
floorplanner'' that considers both the impact of wire delay and the
architectural behavior, namely the inter-module communication,
to reduce the latency of frequent routes inside a
processor and to maintain performance scalability.
Based on our simulation results, the profile-guided
method shows a 5% to 40% average IPC improvement when clock
frequency is fixed. From the perspective of instruction throughput
(in BIPS), our floorplanner is much more scalable than
a conventional wire length based floorplanner.